1. Field of the Invention
This invention relates generally to processor-based systems, and, more particularly, to a matrix algorithm for scheduling operations in processor-based systems.
2. Description of the Related Art
Conventional processor-based systems typically include one or more processing elements such as a central processing unit (CPU), a graphical processing unit (GPU), an accelerated processing unit (APU), and the like. The processing units include one or more processor cores that are configured to access instructions and/or data that are stored in a main memory and then execute the instructions and/or manipulate the data. Each processor core includes a floating point unit that is used to perform mathematical operations on floating point numbers when required by the executed instructions. For example, conventional floating-point units are typically designed to carry out operations such as addition, subtraction, multiplication, division, and square root. Some systems can also perform various transcendental functions such as exponential or trigonometric calculations. Floating-point operations may be handled separately from integer operations on integer numbers. The floating-point unit may also have a set of dedicated floating-point registers for storing floating-point numbers.
High-performance out-of-order execution microprocessors can select operations for execution out of program order. Out-of-order processing can be used to improve the performance of a processor-based system as long as the dependencies between the operations are respected and accounted for by the microprocessor. For example, a floating-point unit may be able to perform floating-point operations in an order that is different than the order that is specified in the program code. However, before the floating-point unit can execute an operation, the floating-point unit must determine whether all the operands of the operation are ready, whether any other operations are blocking the current operation, whether any pipeline hazards exist, and whether any other conditions would cause the operation to complete incorrectly. The floating-point unit must also schedule the operation. Conventional instruction scheduling approaches can slow down logical elements in the processor system, such as the floating-point unit, leading to timing issues that degrade the performance of the system.